Monolithic integrated circuits with multiple types of embedded non-volatile memory devices

ABSTRACT

Circuits are described that use metallization on both sides techniques to integrate two different types of non-volatile embedded memory devices within a single monolithic integrated circuit device. In an embodiment, a monolithic integrated circuit structure is provided that includes a device layer having one or more logic transistors. A front side interconnect layer is provided above the device layer, as seen in a vertical cross-section taken through the monolithic integrated circuit from top to bottom. A back side interconnect layer is provided below the device layer, as seen in the vertical cross-section. A first type of non-volatile memory device is provided in the front side interconnect layer, and a second type of non-volatile memory device different from the first type of non-volatile memory device is provided in the back side interconnect layer. A back side contact may be used to connect the device layer to a back side interconnect layer.

BACKGROUND

Integration of non-volatile memory cells on a same substrate as logictransistors is often referred to as “embedded non-volatile memory” or“eNVM.” Embedding non-volatile memory on a same substrate as logictransistors improves computational speed and efficiency compared tomemory devices and semiconductor devices that are disposed on separatesubstrates and that therefore communicate through an inter-substratebus. While common types of integrated memory devices include eDRAM andSRAM, various types of resistive and magneto-resistive random accessmemory (RRAM and MRAM, respectively) devices are of increasing interest,particularly for embedded non-volatile memory (eNVM) devices. Generally,MRAM devices store a bit of data by magnetizing or de-magnetizing a“free” layer of a magneto-resistive device. The electrical resistance ofthe free layer relative to an associated magnetized “fixed” or“reference” layer is then used to determine a binary value of “1” or “0”in the MRAM device. An analogous resistive, non-magnetic mechanism isused for RRAM devices. Because resistive data storage does not requireperiodic electrical refreshment, as do memory storage devices that usean electrical charge such as eDRAM and SRAM, the data stored in the RRAMand MRAM devices persists even after power is removed from the circuit.Examples of MRAM memory devices include, but are not limited to, spinhall effect magnetic random access memory (SHE-MRAM), and spin transfertorque MRAM (STT-MRAM).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic cross-sectional illustration of an example spintorque transfer magneto-resistive random access memory device (STT-MRAM)within an integrated circuit taken along a direction parallel to a gateof a transistor, in accordance with an embodiment of the presentdisclosure.

FIG. 1B is a schematic cross-sectional illustration of an example spinhall effect magneto-resistive random access memory device (SHE-MRAM)within an integrated circuit taken along a direction parallel to a gateof a transistor, in accordance with an embodiment of the presentdisclosure.

FIG. 1C is a schematic illustration of an example resistive randomaccess memory device (RRAM) within an integrated circuit, in accordancewith an embodiment of the present disclosure.

FIG. 2 is a flow diagram of an example method for fabricating amonolithic integrated circuit including two or more different types ofeNVM devices, using metallization on back side (“MOBS”) fabricationtechniques, in accordance with an embodiment of the present disclosure.

FIGS. 3A-C are cross-sectional views of a series of integrated circuitstructures taken along a direction parallel to a gate of a transistor ofan integrated circuit structure, the views illustrating formation anintegrated circuit that includes an STT-MRAM eNVM device and a SHE-MRAMeNVM device fabricated on an opposite side of a device layer accordingto the method shown in FIG. 2, in accordance with an embodiment of thepresent disclosure.

FIG. 4A is a cross-sectional view taken along a direction parallel to agate of a transistor of an integrated circuit fabricated according tothe method shown in FIG. 2 that includes an STT-MRAM device and an RRAMdevice, in accordance with another embodiment of the present disclosure.

FIG. 4B is a cross-sectional view taken along a direction parallel to agate of a transistor of an integrated circuit fabricated according tothe method shown in FIG. 2 that includes an SHE-MRAM device and an RRAMdevice, in accordance with another embodiment of the present disclosure.

FIG. 4C is a cross-sectional view taken along a direction parallel to agate of a transistor of an integrated circuit fabricated according tothe method shown in FIG. 2 that illustrates a location of a source lineand a bit line corresponding to each of the first eNVM device type andthe second eNVM device type, in accordance with an embodiment of thepresent disclosure.

FIG. 5 is a depiction of a computing system configured in accordancewith an embodiment of the present disclosure.

The figures depict various embodiments of the present disclosure forpurposes of illustration only. Numerous variations, configurations, andother embodiments will be apparent from the following detaileddiscussion.

DETAILED DESCRIPTION

Techniques are disclosed for forming integrated circuits using“metallization on both sides” or “MOBS” so as to integrate two differenttypes of embedded memory devices within a single monolithic integratedcircuit. By using MOBS techniques, an embedded non-volatile (“eNVM”)memory device of a first type can be integrated within a front sideinterconnect layer above a given device layer, and an eNVM memory deviceof a second type different from the first type can be integrated withina back side interconnect layer below the given device layer. The twostructures including the diverse eNVM memory device types can be formedon separate substrates, and are then joined (one of the substrates canbe removed or at least partially removed to facilitate the joiningprocess) using MOBS processing, thereby placing the structures anddevices thereon, including the two different types of eNVM devices, intoelectrical contact or an otherwise functional integrated circuitarrangement. An alternative characterization of this arrangement issimply a substrate having a device layer, a first side above the devicelayer and a second side that is on an opposite side of the device layerfrom the first side. A first type of eNVM device is disposed on thefirst side of the substrate (“above” the device layer as shown in thefigures although it will be appreciated this term is used forconvenience only). A second type of eNVM device different from the firsttype is disposed on the second side of the substrate (“below” the devicelayer as shown in the figures). Each eNVM device is associated with abit line and a source, each of which is disposed on one of the firstsubstrate or the second substrate.

The disclosed techniques may provide various advantages over integratedcircuits that include only a single type of memory device integratedwith semiconductor devices on a substrate. For example, becausedifferent types of eNVM devices have different advantages in differentoperational regimes, integrating at least two different types of eNVMdevices within single monolithic integrated circuit can improve theoverall computational efficiency of the integrated circuit by increasingdata access efficiency and/or computational efficiency over a broaderrange of operational states.

It is noted that front side and back side designations are relative to agiven orientation of the device layer, which may change during the MOBSprocessing scheme, as the device layer is inverted or flipped toaccommodate further processing. Further note that when the monolithicintegrated circuit structure is inverted, such that the device layer iseffectively pointing down, the channels of the transistor devices inthat device layer are, relatively speaking, above their respectivegates, rather than below the gates as typically depicted. To this end,reference herein to “front side” or “back side” or “above” or “below” or“top” or “bottom” or “top side” or “bottom side” is not intended tonecessarily implicate a limitation as to orientation of the monolithicstructure. Rather, such terminology is simply used in a relative senseto consistently describe the structure as it exists in any oneparticular orientation. In reality, the monolithic structure can beturned and inverted and otherwise oriented as desired for a givenapplication, and the relative terminology used herein can simply beadjusted to that actual orientation and still equally apply.

General Overview

As will be appreciated in light of this disclosure, each type of eNVMdevice (e.g., RRAM and MRAM devices) has a different operational regimein which it may be more efficient and/or preferred. With the currentlogic process technology, however, different types of eNVM devices can'tbe integrated in the same substrate due to the conflicting requirementof manufacturing process for each type of eNVM technology. For example,as shown in FIGS. 1A and 1B, and explained below in more detail, thesequence of the layers in an STT-MRAM device 102 relative to a devicelayer is opposite of that of a sequence of layers in an SHE-MRAM device160. For example, the sequence of a free layer and a reference layer(and thus the order in which the layers are formed during fabrication)are reversed in an STT-MRAM device (illustrated in FIG. 1A) relative toa device layer compared to an SHE-MRAM device (illustrated in FIG. 1B).This is because a free layer of a magnetic tunnel junction (“MTJ”)transistor of STT-MRAM is placed on a side of a fixed layer oppositethat of a device layer (i.e., proximate to a “higher” interconnectlevel) to improve device performance and manufacturing yields. Incontrast, a free layer of an MTJ transistor of SHE-MRAM is placed“under” a fixed layer (i.e., proximate to a device layer and “lower”interconnect levels) so as to place free layer in contact with a spinfilter. Forming two different compositions of layers for these differenttypes of eNVM devices at a same interconnect layer within an integratedcircuit makes fabrication of these devices challenging. Moreover, insome cases the different types of materials used in the various devices,the thermal processing applied to one type of an MRAM or RRAM device isnot necessarily compatible with other types of eNVM devices. Forexample, the thermal processing used in the fabrication of an STT-MRAMdevice can degrade the materials that may be used to fabricate anSHE-MRAM device. Similarly, RRAM devices are generally not fabricatedwith either STT-MRAM or SHE-MRAM devices due to differences in thethermal processing of these devices. Another impediment to integratingmultiple (i.e., two or more) types of eNVM devices on a same substrateis that the interconnects used to read data from and write data to theeNVM devices are generally configured to occupy similar locations withina back end layer of an integrated circuit. For example, generally formemory devices that are designed as “one transistor, one resistor”devices (1T/1R devices for brevity), it is preferred to connect theresistor (in this case, the MRAM device) to a corresponding transistorusing, in part, low resistance interconnects. This generally involvesinterconnects (e.g., metal lines and/or vias) having dimensions largerthan those found at interconnect levels more proximate to the devicelevel. These relatively large interconnects have a lower electricalresistance compared to dimensionally smaller interconnects moreproximate to a device level. However, the interconnects to differenttypes of eNVM devices would compete for limited space within the sameinterconnect layers, thus further prohibiting integration of multipledifferent types of eNVM devices. This issue is further complicated forcertain combinations of eNVM devices that cannot use a commoninterconnect because the signals conducted by the interconnect aredifferent. That is, a common interconnect path may not be used in somecases because a read signal appropriately provided to a first type ofeNVM device may not be appropriate to provide to a connected, butdifferently configured, second type of eNVM device.

Thus, and in accordance with an embodiment of the present disclosure,techniques are provided for forming monolithic integrated circuits thatinclude two different types of eNVM devices. Example embodiments includemonolithic integrated circuits that include any of the followingcombinations: (1) SHE-MRAM and STT-MRAM; (2) SHE-MRAM and RRAM; and (3)STT-MRAM and RRAM. More generally, other embodiments may include adevice layer having front side interconnect configured with a first typeof eNVM device, and a back side interconnect configured with a secondtype of eNVM device different from the first type. These various exampleembodiments are fabricated using “metal on both sides” or “MOBS”techniques. In this way, the different fabrication processes andmaterial selections for different types of eNVM devices can be performedso as to integrate two different types of eNVM devices within amonolithic integrated circuit while avoiding the complications andissues indicated above.

The disclosed techniques of forming a monolithic integrated circuit thatincludes any two eNVM devices (e.g., SHE-MRAM, STT-MRAM, and RRAM) mayprovide various advantages. For example, the example embodimentsdescribed herein can reduce power consumption of an integrated circuitwhile improving performance of the integrated circuitry by enablingdirect code execution by the integrated circuit. Furthermore, includingany two eNVM devices (e.g., SHE-MRAM, STT-MRAM, and RRAM) within anintegrated circuit provides different types of eNVM devices havingdifferent preferred operational regimes. Thus, the integrated circuit asa whole can perform computations more efficiently over a broader rangeof operational conditions. These broader ranges of conditions caninclude factors such as memory density, data retention at hightemperatures, power consumption, and a speed at which data is written toor read from each of the eNVM devices. Other advantages will be apparentin light of this disclosure. Also, numerous variations andconfigurations will be apparent in light of this disclosure.

Embedded Non-Volatile Memory Device Configurations

FIGS. 1A, 1B, and 1C illustrate example configurations of embeddednon-volatile memory devices STT-MRAM, SHE-MRAM, and RRAM, respectively.These three device types are referred to herein collectively as “eNVM,”although as will be appreciated, the embodiments described herein may beapplicable to different types of embedded memory devices. The eNVMconfigurations are presented for context prior to describing theintegration of two different types of eNVM devices within a singlemonolithic integrated circuit as shown in in FIGS. 2, 3A-3C, 4A, and 4B.

Turning to FIG. 1A, an integrated circuit (“IC”) 100 is shown thatincludes an STT-MRAM embedded non-volatile memory device 102 (“STT-MRAM”device for brevity) in electrical contact with other elements of the IC100. The IC 100 is described below for convenience as having twoportions: a device layer 112 and a back end layer 126. Each of theselayers, the corresponding elements within each layer, including theSTT-MRAM device 102, are described below in detail.

The device layer 112, comprising a semiconductor device 108 some or allof which is encapsulated in interlayer dielectric (ILD) 106, isfabricated on a substrate 104.

Examples of the substrate 104 include single crystal silicon substrates,whether oriented in any of the [111] direction, the [110] direction, orthe [100] direction. Other types of substrates can be substituted forsingle crystal silicon. For example, the substrate 104 may also includea buried oxide (BOX) layer, or be a semiconductor-on-insulator (or “XOI”where X is any semiconductor) substrate. One specific XOI substrateexample includes a blanket layer of silicon dioxide (SiO₂) with asilicon (Si) substrate. The presence or absence of an underlying oxideor insulator may affect the performance of other semiconductor devicesin an integrated circuit associated with the resonators of the presentdisclosure, but generally will not affect the fabrication or performanceof the MRAM memory devices described herein.

The ILD 106 is used to provide electrical insulation and mechanicalintegrity to semiconductor devices 108 fabricated within and/or on thesubstrate 104. Example insulator materials that can be used for the ILD106 include, for instance, nitrides (e.g., Si₃N₄), oxides (e.g. SiO₂,Al₂O₃), oxynitrides (e.g., SiO_(x)N_(y)), carbides (e.g., SiC),oxycarbides, polymers, silanes, siloxanes, or other suitable insulatormaterials. In some embodiments, the ILD 106 is implemented withultra-low-k insulator materials, low-k dielectric materials, or high-kdielectric materials depending on the application. Example low-k andultra-low-k dielectric materials include porous silicon dioxide, carbondoped oxide (CDO), organic polymers such as perfluorocyclobutane orpolytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicatessuch as silsesquioxane, siloxane, or organosilicate glass. Examples ofhigh-k dielectric materials include, for instance, hafnium oxide,hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide,zirconium oxide, zirconium silicon oxide, tantalum oxide, titaniumoxide, barium strontium titanium oxide, barium titanium oxide, strontiumtitanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalumoxide, and lead zinc niobate. Techniques for forming the ILD 106 can beany of a wide range of suitable deposition techniques, including but notnecessarily limited to: physical vapor deposition (PVD); chemical vapordeposition (CVD); spin coating/spin-on deposition (SOD); and/or acombination of any of the aforementioned. Other suitable configurations,materials, deposition techniques, and/or thicknesses for ILD 106 willdepend on a given application and will be apparent in light of thisdisclosure.

The semiconductor device 108, in this example, includes a source 116, achannel region 118, a drain 120, and a gate 124. Although the simpleplanar transistor depiction used to illustrate the semiconductor device108 is presented for convenience, it will be appreciated that non-planarconfigurations of semiconductor device 108 are also possible. Examplesof semiconductor devices that can be formed in device layer 112 include,but are not limited to, planar field effect transistors (FETs), andnon-planar FETS (e.g., finFETs or nanowire FETs), capacitors (e.g.,embedded DRAM (eDRAM) capacitors), DRAM devices, and SRAM devices, amongothers.

As will be appreciated, the actual devices implemented in the devicelayer 112 will depend on the target application and function of theintegrated circuit 100, and the present disclosure is not intended to belimited to any particular application or functional circuitry. Rather,the techniques provided herein can be used with any number of devicelayer 112 configurations. These devices, often fabricated on and/orwithin a semiconducting substrate 104 are in electrical contact with atleast one interconnect (described below). Fabrication of thesemiconductor device 108 can be accomplished using one or more of ionimplantation, epitaxial growth, sputtering, chemical vapor deposition(CVD), atomic layer deposition (ALD), photolithography, planarizationtechniques (e.g., chemical and/or mechanical polishing), among others.The source 116, channel 118, drain 120, and gate 124 need not bedescribed in further detail.

Regardless of the configuration, the semiconductor device 108, and othersemiconductor devices within the integrated circuit 100 and/or withinother integrated circuits not shown in FIG. 1A, is connected to one ormore interconnect structure(s). In the example shown in FIG. 1A, theseinterconnect structure(s) are disposed within a back end layer 126,which in this example comprises three interconnect layers 130, 132, and150.

The interconnect layers 130, 132, and 150 are each shown as includingone or two interconnects, whether a via or a conductive line or both. Itwill be appreciated that this depiction is for convenience only and thatinterconnect layers often include a plurality of one or both of vias orconductive lines. Regardless of the number or type of interconnectswithin an interconnect layer, interconnects, such as vias 128, 136 andconductive metal lines 131 and 152 connect a semiconductor device, suchas semiconductor device 108 to other semiconductor devices elsewherewithin an integrated circuit, or connect a semiconductor device to anelectrical contact at an upper or lower layer of the integrated circuit100, through a network of selectively connected vias and conductivelines. The vias and conductive lines are insulated from one another withILD, which can be fabricated using any of the materials described above.With each successive layer of interconnect structures, generally greaternumbers of semiconductor devices 108 can be connected together.Ultimately, the semiconductor devices, through a series of interconnectstructures, are placed in electrical contact with an input and/or anoutput so that instructions and/or data can be received at and/or sentfrom the integrated circuit 100. The interconnect layers 130, 132, and150, and the interconnect structures therein, can be fabricated usingany of a variety of techniques that include, but are not limited toepitaxial growth, sputtering, chemical vapor deposition (CVD), atomiclayer deposition (ALD), photolithography and other patterningtechniques, and planarization techniques (e.g., chemical and/ormechanical polishing).

The interconnect layer 132, in the example shown in FIG. 1A, includes anSTT-MRAM embedded non-volatile memory device 102. The STT-MRAM device102 includes a reference layer 140, a barrier layer 144, and a freelayer 148.

As indicated above, an STT-MRAM device, such as the device 102 shown inFIG. 1A, stores a bit of data by controlling an electrical resistancebetween the reference layer 140 and the free layer 148. This electricalresistance is changed by changing the spin polarization, and thus theangular momentum, of electrons within the free layer 148 relative tospin polarization of electrons in the reference layer 140. It will beappreciated that while STT-MRAM device 102 is shown as including one ofeach of the reference layer 140, barrier layer 144, and the free layer148, other configurations of STT-MRAM devices may include many of eachone of these layers. Furthermore, it will be appreciated that theSTT-MRAM device 102 may be disposed within any interconnect layer (e.g.,M1, M2, M3, M4) within the back end layer 126, although often an MTJ ofan STT-MRAM devices are disposed at or above M3 (i.e., the third levelof interconnect above a device layer, although alternativeconfigurations in which the MTJ of a STT-MRAM device is disposed at M3below a device layer will also be appreciated) so as to avoid exposingthe STT-MRAM layers to the higher temperatures used earlier stages of IC100 fabrication.

Continuing with the description of the STT-MRAM device 102, thereference layer 140 can, in some examples, be fabricated from a materialor a stack of materials that maintains a magnetization polarity (i.e., aspin of electrons) and is a “hard” magnetic material having a magneticcoercivity higher than that of the free layer 148. Types of materialsused to fabricate the reference layer 140 include permanent magneticmaterials, such as ferromagnetic materials. In one example, thereference layer 140 is fabricated from a single layer of cobalt ironboron (CoFeB). In another example, the reference layer 140 is composedof a stack of materials that include a cobalt iron boron (CoFeB) layer,a ruthenium (Ru) layer, and a cobalt iron boron (CoFeB) layer. In anexample, not shown, a synthetic antiferromagnet (SAF) layer is disposedon or adjacent to the reference layer 140. The reference layer 140 canbe deposited using any of a variety of techniques including, but notlimited to, chemical vapor deposition, atomic layer deposition,sputtering, among other deposition techniques.

The barrier layer 144 is generally a dielectric material configured topermit electrons to tunnel through it into the free layer 148. Thebarrier layer 144 can facilitate selective tunneling so that electronshaving a preferred spin polarity can tunnel from the reference layer 140through the barrier layer 144 into the free layer 148. This selectivetunneling can be used to control the magnetization polarity of electronsin the free layer 148, and thus control the resistance of the STT-MRAMdevice 102. In some examples the barrier layer 144 is fabricated frommagnesium oxide (MgO) or aluminum oxide (Al₂O₃) although otherdielectric materials may also be used. The barrier layer 144 can bedeposited using any of a variety of techniques including, but notlimited to chemical vapor deposition, organometallic chemical vapordeposition, atomic layer deposition, sputtering, among other depositiontechniques.

The free layer 148 is fabricated from a material that can switch betweenelectron spin states, changing its magnetization polarity relative tothe reference layer 140 and thus changing the resistance of the device.The free layer 148 can be fabricated from ferromagnetic materialsincluding, but not limited to, cobalt iron (CoFe) or cobalt iron boron(CoFeB). The ferromagnetic material of the free layer 148 can bedeposited using any of a variety of techniques including, but notlimited to, epitaxial deposition, atomic layer deposition, so as toproduce a single crystal ferromagnet having a uniform magnetizationpolarity.

FIG. 1B illustrates an integrated circuit 158 similar to the integratedcircuit 100 except that the integrated circuit 158 includes a SHE-MRAMeNVM device 160 (“SHE-MRAM device” for brevity) that is in electricalcontact with other elements of the IC 158.

Many of the elements of the integrated circuit 158 are analogous tothose shown in the integrated circuit 100, including the substrate 104,the device layer 112, ILD 106, interconnect layers 130, 132, 150, andinterconnect structures 128, 131, and 152. These elements need nofurther explanation.

Unlike the integrated circuit 100, the integrated circuit include theSHE-MRAM device 160, which in turn includes a spin filter 164, a freelayer 168, a barrier layer 172 and a reference layer 176.

SHE-MRAM devices relies on the “spin Hall effect” in which electronswith different spins can be directed into different directions as aresult of the different angular momentum of the different spins. Theeffect can be used to control current applied to various layers withinthe SHE-MRAM 160.

The spin filter 164 is used to “polarize” (i.e., preferentially impartone type of spin (e.g., “up”) onto a majority of electrons compared to asecond type of spin (e.g., “down”). In examples, the spin filter 164 canbe fabricated from any of the following: β-Tantalum (β-Ta); β-Tungsten(β-W); platinum (Pt); a Ag/Bi bilayer; BiSe; MoS₂; and Cu doped with Bi,iridium (Ir), tungsten (W), or any of the elements of 3d, 4d, 5d and 4f,5f periodic groups in the Periodic Table which may exhibit high spinorbit coupling. The spin filter 164 can be deposited using any of avariety of techniques including, but not limited to, chemical vapordeposition, organometallic chemical vapor deposition, atomic layerdeposition, sputtering, among other deposition techniques.

The free layer 168 is, like the reference layer 176 described below,fabricated from a magnetic material, and in particular a ferromagneticmaterial. However, in some examples the material of the free layer 168is selected to have a lower magnetic coercivity than that of thereference layer 176, and thus can be magnetized or demagnetized withless force needed compared to high coercivity materials. In someexamples, the free layer 168 can be fabricated from cobalt iron (CoFe)or cobalt iron boron (CoFeB). The free layer 168 can be deposited usingany of a variety of techniques including, but not limited to, chemicalvapor deposition, organometallic chemical vapor deposition, atomic layerdeposition, sputtering, among other deposition techniques.

The barrier layer 172 provides a resistive barrier between the freelayer 168 and the reference layer 176. Upon application of a sufficientelectrical field, a difference in resistance between the free layer 168and the reference layer 176 can be identified so as to read data fromthe SHE-MRAM device 160. In some examples, the barrier layer 172 isfabricated from magnesium oxide (MgO) and is configured to enableselective tunneling of polarized electrons from the free layer 168through the barrier layer 172 and into reference layer 176. The barrierlayer 172 can be deposited using any of a variety of techniquesincluding, but not limited to, chemical vapor deposition, organometallicchemical vapor deposition, atomic layer deposition, sputtering, amongother deposition techniques.

The reference layer 176 can be a magnetic layer having a fixedmagnetization. As indicated above in the context of the STT-MRAM, thereference layer 176 generally is fabricated from a material having ahigher magnetic coercivity that the free layer 168. As such, thereference layer 176 can be fabricated from as a magnetized ferromagneticmaterial. In some examples, the reference layer 176 is fabricated fromcobalt iron boron (CoFeB). In another example, the fixed magnetic layeris fabricated as a stack of a cobalt iron boron (CoFeB) layer, aruthenium (Ru) layer, and another cobalt iron boron (CoFeB) layer. Thereference layer 176 can be deposited using any of a variety oftechniques including, but not limited to, chemical vapor deposition,organometallic chemical vapor deposition, atomic layer deposition,sputtering, among other deposition techniques.

While not shown, some examples of SHE-MRAM devices may includeadditional layers, such as a synthetic anti-ferro-magnet (SAF)(fabricated from CoFe and ruthenium), and an antiferromagnet layer.

FIG. 1C illustrates an integrated circuit 180 similar to the integratedcircuits 100 and 158 except that the integrated circuit 180 includesRRAM eNVM device 184 (“RRAM device” for brevity) that is in electricalcontact with other elements of the IC 180.

Many of the elements of the integrated circuit 180 are analogous tothose shown in the integrated circuits 100 and 158, including thesubstrate 104, the device layer 112, ILD 106, interconnect layers 130,132, 150, and interconnect structures 128, 131, and 152 and need nofurther explanation.

As indicated above, RRAM devices such as the one shown in FIG. 1C,stores a bit of data by changing an electrical resistance of the deviceusing a memristor. The RRAM device can change a high-resistance state(HRS), which may be representative of an “off” or “0” bit and alow-resistance state (LRS), which may be representative of an “on” or“1” bit. The RRAM device 184 includes a first (1^(st)) electrode 186, aswitching layer 188, an optional oxygen exchange layer (OEL) 190, and asecond (2^(nd)) electrode 192.

The first electrode 186 and the second electrode 192 place the RRAMdevice 184 into electrical contact with other elements of the integratedcircuit 180, including a corresponding transistor of this 1T/1R memorydevice. In some examples, the first electrode 186 and the secondelectrode 192 include at least one of: disulfur dinitride (S₂N₂);titanium nitride (TiN); tantalum nitride (TaN); copper (Cu); tungsten(W); titanium (Ti); one or more noble metals, such as ruthenium (Ru),rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), iridium (Ir),platinum (Pt), and gold (Au); and/or any other suitable material orcombination of materials, as will be apparent in light of thisdisclosure.

The switching layer 188, which has a lower conductivity than either ofthe first electrode 186 or the second electrode 192, can improve thestability and/or retention of a bit stored within the RRAM device 184.The switching layer 188 can be fabricated from one or more of thefollowing materials: a metal oxide, such as hafnium oxide (HfO_(x)),titanium oxide (TiO_(x)), nitrogen oxide (NiO_(x)), tungsten oxide(WO_(x)), tantalum oxide (TaO_(x)), zirconium oxide (ZiO_(x)), vanadiumoxide (VO_(x)), copper oxide (CuO_(x)), aluminum oxide (AlO_(x)); ametal alloy oxide; and/or any other suitable material, as will beapparent in light of this disclosure.

In some embodiments, the optional oxygen exchange layer (OEL) 190, whenpresent, may include at least one of: hafnium (Hf); titanium (Ti);tantalum (Ta); and/or any other suitable material or combination ofmaterials. In some such embodiments, OEL 190 may be present in RRAMdevice 184 to, for example, increase flexibility in incorporating theother materials. For instance, in some embodiments, OEL 190 may bepresent to affect the switching mechanism of the RRAM device 184, suchas to help provide a more stable switching mechanism, for example.

The materials of the switching layer 188 and the optional oxygenexchange layer 190 may be formed by, for example, any one or more ofatomic layer deposition, chemical vapor deposition, organometallicchemical vapor deposition, among others.

In some embodiments one or more of the layers of the RRAM device 184 mayhave a multilayer structure. For instance, in some embodiments,switching layer 188 may include two material layers that may or may notinclude grading (e.g., increasing and/or decreasing) the content of atleast one material throughout the multilayer structure.

Methodology and Architecture

Having introduced various example eNVM device structures 102, 160, and184 and the challenges regarding integration of more than one type ofeNVM device on a substrate, a method 200 that includes using“metallization on both sides” (“MOBS”) techniques is described in thecontext of FIG. 2, with concurrent reference to device cross-sectionalviews shown in FIGS. 3A-3C, for fabricating a monolithic integratedcircuit that overcomes the challenges indicated above. The devicecross-sectional views shown in FIGS. 3A-3C are taken parallel to a gateof a logic transistor.

The method 200 includes (1) a front side substrate sub-process 204 forfabricating a first type of eNVM device on a front side (or “first”)substrate and (2) a back side (or “second”) substrate sub-process 208that includes fabricating a second type of eNVM device different fromthe first type on a back side substrate. The front side substrate andthe back side substrate are then joined in a substrate joiningsub-process 210, thus placing the first type of eNVM device on the frontside substrate into electrical contact with the back side substrate andthe second type of eNVM device thereon. The method 200 is describedbelow in the context of each of these sub-processes 204, 208, and 210for convenience. It will be appreciated that the following explanationis not intended to ascribe an order to the various sub-processes.

The front side substrate sub-process 204 of the method 200 begins byproviding 216 a front side substrate 300 and forming 220 a device layer304 thereon using any of the techniques described above in the contextof the device layer 112 (e.g., patterning, ion implantation, depositionand/or growth of various conducting and semiconducting layers,deposition of an encapsulating ILD layer). As shown in FIG. 3A, thedevice layer includes a logic transistor 312 (that includes a source316, a channel 318, a drain 320, and a gate 324) similar to the logictransistors shown in FIGS. 1A-1C and described above. The techniques canbe used to form any configuration and/or any type of semiconductordevice also described above in the context of the semiconductor device108.

Furthermore, as part of forming 220 the device layer, and as a componentof MOBS processing, a back side contact 302 shown in FIG. 3A is alsoformed 222. This back side contact 302 is disposed on a side of thedevice layer 304 that is opposite a side on which a back end layer 340is formed, as described below. The back side contact 302, which can be adeep diffusion contact, is configured to enable electrical contactbetween one or more of the logic transistor 312, an interconnect of thefront side substrate, and a eNVM device of the front side substrate andone or more of these on a back side substrate, as described below inmore detail. The back side contact 302, as mentioned above, can beformed 222 by a deep diffusion contact in which a type of ion isimplanted (and diffused) deep within the substrate so as to form aconductive region. Alternatively, the back side contact 302 can beformed 222 as a metal interconnect analogous to a via or metal line inan interconnect layer.

The device layer 304 of the front side substrate 300 is completed byencapsulating at least the logic transistor 312 in an ILD layer 328 andplanarizing the ILD layer 328.

Interconnects 334, 335 are formed 224 in one or more interconnect layers332, 336, 338. The interconnects 334, 335 and the interconnect layers332, 336, 338 are formed 224 using any of the materials and/ortechniques described above in the context of the back end layer 126,156, 182 described above.

Continuing with FIG. 3A, a first type of eNVM device (i.e., one ofSHE-MRAM, STT-MRAM, and RRAM) is formed 228 within at least one of theinterconnect layers 332, 336, 338, again using any of the materials anddeposition techniques already described above in the context of any ofFIGS. 1A, 1B, and 1C. In the example shown in FIG. 3A, the first type ofeNVM device is a SHE-MRAM device 342 in the interconnect layer 338. Insome examples, the MTJ of the SHE-MRAM is disposed at “M3” (the thirdinterconnect level above, or in some examples not shown, below a devicelayer) and a bit line is disposed at “M4” (whether above or below adevice layer). A source line of the SHE-MRAM, is disposed at the firstlevel of interconnect on the back side substrate 350. While the sourceline of the SHE-MRAM is omitted from FIGS. 3B and 3C for clarity, thearrangement of bit lines and source lines for the various eNVM devicesof the present disclosure is shown in FIG. 4C and described below. Itwill be appreciated that any of the eNVM devices described above, amongothers, can be fabricated within the back end layer 340 of the frontside substrate 300 using patterning and deposition techniques describedabove.

With reference to FIG. 3B, the back side substrate sub-process 208beings by providing 215 a back side substrate 350 that can be a same ora different composition and/or structure as the front side substrate300. For example, the front side substrate provided 216 could include aSOX substrate to enhance the performance of a semiconductor devicethereon, whereas the back side substrate provided 215 may be a simplesilicon single crystal substrate. Regardless, upon providing 215 theback side substrate 350, at least one interconnect layer 354, 358 (whichinclude interconnects 356, interconnect bit line 357, an interconnectsource line for the SHE-MRAM device 342 (omitted for clarity, butillustrated in FIG. 4C) and ILD) is formed 223 on the back sidesubstrate 350. At least one of the interconnects formed 223 isconfigured to be placed into electrical contact with the back sidecontact 302 of the front side substrate 300.

Also within at least one of the interconnect layer 354, 358 is a secondtype of eNVM device different from the first type of device, in thiscase an STT-MRAM device 360, is formed 227 using patterning anddeposition techniques described above. In an example, a bit line 357 andMTJ corresponding to the STT-MRAM device 360 correspond to M-2 and M-3of the back side substrate, respectively. Because the bit lines 335, 357of the SHE-MRAM 342 and STT-MRAM 360 devices, respectively, are onphysically separate interconnect layers of the front side substrate andback side substrate, respectively, thus using different interconnectlayers and structures, the resistances of each interconnect structurecan be optimized for the corresponding device. Source lines (not shownin FIG. 3A-3C for clarity, but illustrated in FIG. 4C) for each deviceare similarly disposed on different interconnect layers and thus mayalso be optimized for performance of the corresponding device.

The substrate joining sub-process 210 is performed so as to place thefront side substrate 300 and the back side substrate 350, and the twodifferent types of eNVM devices thereon, into electrical contact. In oneexample, this can be accomplished by first removing 236 bulk substratematerial from the exposed substrate 300 surface so as to expose the backside contact 302. This has the effect preserving the front side back endlayer 340 and exposing the back side contact 302 for subsequentelectrical contact with a back side substrate 350.

Removing material can be accomplished by one or more of grinding,etching, and/or chemical mechanical polishing/planarizing (CMP), with orwithout the use of an etch stop layer (e.g., a crystalline or amorphousinsulator like silicon on insulator (SOI), for example). Such asubstrate material removal process is colloquially referred to as “backside reveal,” as it reveals the back side or underside of the devicelayer. The subsequent processing can include forming additional contacttrenches in the revealed back side and depositing metal contacts in theback side contact trenches using patterning techniques described above.

The front side substrate 300 and the backside substrate 350 are thenplaced 240 into electrical contact using, for example, the back sidecontact 302 and a corresponding interconnect 356. Various other elementsof the substrate joining process 210 may be performed (e.g., adheringthe front side substrate 300 and the back side substrate 350, althoughthese need not be discussed herein. The configuration in FIG. 3C can bedescribed as placing a back side interconnect layer “below” the devicelayer shown in FIG. 3A as viewed in the vertical cross-sections of FIGS.3A-3C. As indicated above, “below,” “above” and similar orientationterminology are for convenience of description only and are used todescribe relative location of various devices conveniently in thecontext of the examples illustrated in the figures.

As described above, one benefit of embodiments described herein is theability to connect each of the two eNVM devices to low resistance,dimensionally large interconnects. This benefit is also evident uponinspection of FIG. 3C. As shown, the free layer of the SHE-MRAM device342 is connected to an interconnect bit line 335 and the free layer ofthe STT-MRAM 360 is connected, via an intervening spin filter, to aninterconnect bit line 357. Thus, the performance of each of the two eNVMdevices shown in FIG. 3C is improved by using low resistanceinterconnects 335, 357 to read data from and write data to each of theeNVM devices 342, 360.

FIGS. 4A and 4B each show a different combination of devices preparedusing the method 200. FIG. 4A illustrates an RRAM device 404 and anSHE-MRAM device 408 integrated together. FIG. 4B illustrates an RRAMdevice 404 and a STT-MRAM device 412 integrated together. A bit line 335connects to the RRAM device 404 via the second electrode. A bit line 337connects to the STT-MRAM device 412 via the free layer. The fabricationof the monolithic integrated circuits shown in FIGS. 4A and 4B, and thedevices depicted therein, will be apparent upon reading the presentdisclosure and needs no further explanation.

FIG. 4C illustrates the arrangement of the first type of eNVM device 450on the front side substrate 300, the second type of eNVM device 454 onthe back side substrate 350, and corresponding source lines and bitlines for each device. As indicated above, including more than one typeof eNVM device on a single substrate poses challenges because thevarious interconnects (e.g., source lines and bit lines) for thedifferent types of devices may compete with one another for limitedspace within a back end layer. Embodiments described herein can overcomethis challenge using the MOBS techniques described above, as illustratedin FIG. 4C and further allow resistances of bit lines and source linesassociated with the first type of eNVM device 450 and the second type ofeNVM device 454 to be optimized separately, thus improving individualeNVM device performance and performance of the IC as a whole.

As shown, competition between the various source lines and bit lines ofthe first eNVM device type 450 and the second eNVM device type 454 isresolved by disposing the bit line 460 for the first eNVM device type450 in the interconnect layer 338 of the front side substrate 300 andthe source line 462 for the first eNVM device type 450 in theinterconnect layer 354 of the substrate 350. Similarly, a source line458 for the second eNVM device type 454 is disposed in interconnectlayer 332 of the first substrate 300 and a bit line 456 for the secondeNVM device type 454 is disposed in the interconnect layer 358 of theback side substrate 350. Thus, by disposing a bit line and a source linefor each device on separate substrates, the competition between thedifferent types of devices for space within interconnect layers isresolved.

Use of the techniques and structures provided herein may be detectableusing tools such as: electron microscopy including scanning/transmissionelectron microscopy (SEM/TEM), scanning transmission electron microscopy(STEM), and reflection electron microscopy (REM); composition mapping;x-ray crystallography or diffraction (XRD); energy-dispersive x-rayspectroscopy (EDS); secondary ion mass spectrometry (SIMS);time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; localelectrode atom probe (LEAP) techniques; 3D tomography; or highresolution physical or chemical analysis, to name a few suitable exampleanalytical tools. In particular, in some embodiments, such tools mayindicate the presence of two different types of eNVM devices within asame monolithic integrated circuit fabricated using MOBS techniques.

Example System

FIG. 5 is an example computing system implemented with one or more ofthe integrated circuit structures and embedded non-volatile memorydevices as disclosed herein, in accordance with some embodiments of thepresent disclosure. As can be seen, the computing system 500 houses amotherboard 502. The motherboard 502 may include a number of components,including, but not limited to, a processor 504 and at least onecommunication chip 506, each of which can be physically and electricallycoupled to the motherboard 502, or otherwise integrated therein. As willbe appreciated, the motherboard 502 may be, for example, any printedcircuit board, whether a main board, a daughterboard mounted on a mainboard, or the only board of system 500, etc.

Depending on its applications, computing system 500 may include one ormore other components that may or may not be physically and electricallycoupled to the motherboard 502. These other components may include, butare not limited to, volatile memory (e.g., DRAM), non-volatile memory(e.g., ROM), a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display, a touchscreen display, atouchscreen controller, a battery, an audio codec, a video codec, apower amplifier, a global positioning system (GPS) device, a compass, anaccelerometer, a gyroscope, a speaker, a camera, and a mass storagedevice (such as hard disk drive, compact disk (CD), digital versatiledisk (DVD), and so forth). Any of the components included in computingsystem 500 may include one or more integrated circuit structures ordevices configured in accordance with an example embodiment (e.g., toinclude at least two different types of eNVM devices, as variouslyprovided herein). In some embodiments, multiple functions can beintegrated into one or more chips (e.g., for instance, note that thecommunication chip 506 can be part of or otherwise integrated into theprocessor 504).

The communication chip 506 enables wireless communications for thetransfer of data to and from the computing system 500. The term“wireless” and its derivatives may be used to describe circuits,devices, systems, methods, techniques, communications channels, etc.,that may communicate data through the use of modulated electromagneticradiation through a non-solid medium. The term does not imply that theassociated devices do not contain any wires, although in someembodiments they might not. The communication chip 506 may implement anyof a number of wireless standards or protocols, including, but notlimited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE,GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well asany other wireless protocols that are designated as 3G, 4G, 5G, andbeyond. The computing system 500 may include a plurality ofcommunication chips 506. For instance, a first communication chip 506may be dedicated to shorter range wireless communications such as Wi-Fiand Bluetooth and a second communication chip 506 may be dedicated tolonger range wireless communications such as GPS, EDGE, GPRS, CDMA,WiMAX, LTE, Ev-DO, and others. In some embodiments, communication chip506 may include one or more transistor structures having a gate stack anaccess region polarization layer as variously described herein.

The processor 504 of the computing system 500 includes an integratedcircuit die packaged within the processor 504. In some embodiments, theintegrated circuit die of the processor includes onboard circuitry thatis implemented with one or more integrated circuit structures or devicesas variously described herein. The term “processor” may refer to anydevice or portion of a device that processes, for instance, electronicdata from registers and/or memory to transform that electronic data intoother electronic data that may be stored in registers and/or memory.

The communication chip 506 also may include an integrated circuit diepackaged within the communication chip 506. In accordance with some suchexample embodiments, the integrated circuit die of the communicationchip includes one or more integrated circuit structures or devices asvariously described herein. As will be appreciated in light of thisdisclosure, note that multi-standard wireless capability may beintegrated directly into the processor 504 (e.g., where functionality ofany chips 506 is integrated into processor 504, rather than havingseparate communication chips). Further note that processor 504 may be achip set having such wireless capability. In short, any number ofprocessor 504 and/or communication chips 506 can be used. Likewise, anyone chip or chip set can have multiple functions integrated therein.

In various implementations, the computing system 500 may be a laptop, anetbook, a notebook, a smartphone, a tablet, a personal digitalassistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer,a server, a printer, a scanner, a monitor, a set-top box, anentertainment control unit, a digital camera, a portable music player, adigital video recorder, or any other electronic device that processesdata or employs one or more integrated circuit structures or devicesformed using the disclosed techniques, as variously described herein.

Further Example Embodiments

The following examples pertain to further embodiments, from whichnumerous permutations and configurations will be apparent.

Example 1 includes a monolithic integrated circuit, comprising: a devicelayer including one or more logic transistors; a front side interconnectlayer above the device layer, as seen in a vertical cross-section takenthrough the monolithic integrated circuit from top to bottom; a backside interconnect layer below the device layer, as seen in the verticalcross-section; a first type of non-volatile memory device in the frontside interconnect layer; and a second type of non-volatile memory devicedifferent from the first type of non-volatile memory device in the backside interconnect layer.

Example 2 includes the subject matter of Example 1, wherein at least oneof the first type of non-volatile memory device and the second type ofnon-volatile memory device includes a magnetic tunnel junctiontransistor.

Example 3 includes the subject matter of either of Example 1 or Example2, wherein at least one of the first type of non-volatile memory deviceand the second type of non-volatile memory device comprises a spin halleffect magneto-resistive random access memory device (SHE-MRAM), theSHE-MRAM device comprising a reference layer, a free layer, a barrierlayer disposed between the reference layer and the free layer, and aspin filter on a side of the free layer opposite the barrier layer.

Example 4 includes the subject matter of Example 3, wherein the spinfilter is fabricated from any of the following: β-Tantalum (β-Ta);β-Tungsten (β-W); platinum (Pt); a Ag/Bi bilayer; BiSe; MoS₂; and Cudoped with Bi, iridium (Ir), tungsten (W).

Example 5 includes the subject matter of any of Examples 1 through 4,wherein the reference layer is fabricated from a first magnetic materialhaving a first coercivity; and the free layer is fabricated from asecond magnetic material having a second coercivity less than the firstcoercivity.

Example 6 includes the subject matter of Example 5, wherein the firstmagnetic material and the second magnetic material are both alloys ofcobalt and iron.

Example 7 includes the subject matter of any of Examples 3 to 6, furthercomprising a bit line electrically connected to the SHE-MRAM memorydevice via the free layer.

Example 8 includes the subject matter of Example 2, wherein the magnetictunnel junction transistor is disposed at a third interconnect layereither above or below the device layer; and a bit line is disposed at afourth interconnect layer either above or below the device layer.

Example 9 includes the subject matter of either of Examples 1 or 2,wherein one of the first type of non-volatile memory device and thesecond type of non-volatile memory device comprises a spin torquetransfer magneto-resistive random access memory device (STT-MRAM)comprising a free layer, a barrier layer, and a reference layer.

Example 10 includes the subject matter of Example 9, wherein thereference layer is fabricated from a third magnetic material having athird coercivity; and the free layer is fabricated from a fourthmagnetic material having a fourth coercivity less than the thirdcoercivity.

Example 11 includes the subject matter of Example 10, wherein the thirdmagnetic material and the fourth magnetic material are both alloys ofcobalt and iron.

Example 12 includes the subject matter of any of Examples 9 to 11,further comprising a bit line electrically connected to the STT-MRAMdevice via the free layer.

Example 13 includes the subject matter of Examples 9 to 12, wherein amagnetic tunnel junction transistor of the STT-MRAM device is disposedat a second interconnect layer; and a bit line connected to the STT-MRAMdevice is at a third interconnect layer.

Example 14 includes the subject matter of any of Examples 1 to 13,wherein one of the first type of non-volatile memory device and thesecond type of non-volatile memory device comprises a resistive randomaccess memory (RRAM) device.

Example 15 includes the subject matter of Example 14, wherein the RRAMdevice comprises: a first electrode; a second electrode; and a switchinglayer between the first electrode and the second electrode.

Example 16 includes the subject matter of Example 15, further comprisingan oxygen exchange layer between the switching layer and the secondelectrode.

Example 17 includes the subject matter of Example 15, further comprisinga bit line connected to the RRAM device via the second electrode.

Example 18 includes the subject matter of any of Examples 1 to 17,further comprising: a first bit line connected to the first type ofnon-volatile memory device, the first bit line in a front sideinterconnect layer above the device layer but different from the frontside interconnect layer containing the first type of non-volatile memorydevice; and a second bit line connected to the second type ofnon-volatile memory device, the second bit line in a back sideinterconnect layer below the device layer but different from the backside interconnect layer containing the second type of non-volatilememory device.

Example 19 includes the subject matter of any of Examples 1 to 18,further comprising: a first source line connected to the first type ofnon-volatile memory device, the first source line in a back sideinterconnect layer below the device layer; and a second source lineconnected to the second type of non-volatile memory device, the secondsource line in a front side interconnect layer above the device layer.

Example 20 includes the subject matter of any of Examples 1 to 19,wherein the device layer further includes a back side contact thatelectrically couples a logic transistor of the device layer to a backside interconnect layer below the device layer.

Example 21 includes a computing device that includes the subject matterof any of Examples 1 to 20.

Example 22 includes a method comprising forming a device layer on afirst substrate, the device layer including a logic transistor and aback side contact; forming at least one front side interconnect layerabove the device layer, the at least one interconnect layer including afirst type of non-volatile memory device; forming at least one back sideinterconnect layer on a second substrate, the at least one back sideinterconnect layer including a second type of non-volatile memory devicedifferent from the first type of non-volatile memory device; andconnecting a logic transistor of the device layer to the back sideinterconnect layer via the back side contact.

Example 23 includes the subject matter of Example 22, wherein the firsttype of non-volatile memory device is one of a SHE-MRAM, STT-MRAM, andRRAM and wherein the second type of non-volatile memory device is one ofthe SHE-MRAM, STT-MRAM, and RRAM not the same as the first type ofnon-volatile memory device.

Example 24 includes the subject matter of either of Examples 22 or 23,further comprising forming a bit line in a front side interconnect layerabove the device layer that is connected to the first type ofnon-volatile memory device; and forming a bit line in a back sideinterconnect layer below the device layer that is connected to thesecond type of non-volatile memory device.

Example 25 includes the subject matter of any of Examples 22 to 24further comprising forming a source line in a back side interconnectlayer below the device layer that is connected to the first type ofnon-volatile memory device; and forming a source line in a front sideinterconnect layer above the device layer that is connected to thesecond type of non-volatile memory device.

Example 26 includes the subject matter of any of Examples 22 to 25wherein connecting a logic transistor of the device layer to the backside interconnect layer via the back side contact includes removing oneof the first or second substrates.

Example 27 includes the subject matter of any of Examples 22 to 26further comprising removing bulk substrate material from a back side ofthe first substrate prior to connecting the logic transistor of thedevice layer to the back side interconnect layer via the back sidecontact.

What is claimed is:
 1. A monolithic integrated circuit, comprising: adevice layer including one or more logic transistors; a front sideinterconnect layer above the device layer; a back side interconnectlayer below the device layer; a first type of non-volatile memory devicein the front side interconnect layer above the device layer; a firstsource line for the first type of non-volatile memory device, the firstsource line below the device layer; a second type of non-volatile memorydevice in the back side interconnect layer below the device layer, thesecond type of non-volatile memory device different from the first typeof non-volatile memory device; and a second source line for the secondtype of non-volatile memory device, the second source line above thedevice layer, wherein at least one of the first or second types ofnon-volatile memory devices is connected to a gate of a logic transistorof the one or more logic transistors.
 2. The monolithic integratedcircuit of claim 1, wherein at least one of the first type ofnon-volatile memory device and the second type of non-volatile memorydevice includes a magnetic tunnel junction transistor.
 3. The monolithicintegrated circuit of claim 1, wherein at least one of the first type ofnon-volatile memory device and the second type of non-volatile memorydevice comprises a spin hall effect magneto-resistive random accessmemory device (SHE-MRAM), the SHE-MRAM device comprising a referencelayer, a free layer, a barrier layer disposed between the referencelayer and the free layer, and a spin filter on a side of the free layeropposite the barrier layer.
 4. The monolithic integrated circuit ofclaim 3, wherein the spin filter is fabricated from any of thefollowing: β-Tantalum (β-Ta); β-Tungsten (β-W); platinum (Pt); a Ag/Bibilayer; BiSe; MoS₂; and Cu doped with Bi, iridium (Ir), tungsten (W).5. The monolithic integrated circuit of claim 4, wherein: the referencelayer is fabricated from a first magnetic material having a firstcoercivity; and the free layer is fabricated from a second magneticmaterial having a second coercivity less than the first coercivity. 6.The monolithic integrated circuit of claim 5, wherein the first magneticmaterial and the second magnetic material are both alloys of cobalt andiron.
 7. The monolithic integrated circuit of claim 3, furthercomprising a bit line electrically connected to the SHE-MRAM memorydevice via the free layer.
 8. The monolithic integrated circuit of claim2, wherein: the magnetic tunnel junction transistor is disposed at athird interconnect layer either above or below the device layer; and abit line is disposed at a fourth interconnect layer either above orbelow the device layer.
 9. The monolithic integrated circuit of claim 1,further comprising: a first bit line connected to the first type ofnon-volatile memory device, the first bit line in a front sideinterconnect layer above the device layer but different from the frontside interconnect layer containing the first type of non-volatile memorydevice; and a second bit line connected to the second type ofnon-volatile memory device, the second bit line in a back sideinterconnect layer below the device layer but different from the backside interconnect layer containing the second type of non-volatilememory device.
 10. The monolithic integrated circuit of 1, wherein: thefirst source line is in the back side interconnect layer below thedevice layer; and the second source line in the front side interconnectlayer above the device layer.
 11. The monolithic integrated circuit ofclaim 1, wherein the device layer further includes a back side contactthat electrically couples a logic transistor of the device layer to aback side interconnect layer below the device layer.
 12. A monolithicintegrated circuit, comprising: a device layer including one or morelogic transistors, wherein each of the one or more logic transistorscomprises a corresponding source, a corresponding drain, and acorresponding gate; a front side interconnect layer above the devicelayer; a back side interconnect layer below the device layer; a firsttype of non-volatile memory device in the front side interconnect layerabove the device layer; and a second type of non-volatile memory devicein the back side interconnect layer below the device layer, the secondtype of non-volatile memory device different from the first type ofnon-volatile memory device; wherein the first type of non-volatilememory device is connected to a first one of a source, a drain, or agate; wherein the second type of non-volatile memory device is connectedto a second one of the source, the drain, or the gate; wherein thesecond one of the source, drain, or gate is different from the first oneof the source, drain, or gate; and wherein at least one of the first oneof the source, drain, or gate or the second one of the source, drain, orgate is the gate.
 13. The monolithic integrated circuit of claim 12,wherein: one of the first type of non-volatile memory device and thesecond type of non-volatile memory device comprises a spin torquetransfer magneto-resistive random access memory device (STT-MRAM)comprising a free layer, a barrier layer, and a reference layer; thereference layer is fabricated from a third magnetic material having athird coercivity; and the free layer is fabricated from a fourthmagnetic material having a fourth coercivity less than the thirdcoercivity.
 14. The monolithic integrated circuit of claim 13, whereinthe third magnetic material and the fourth magnetic material are bothalloys of cobalt and iron.
 15. The monolithic integrated circuit ofclaim 12, wherein: one of the first type of non-volatile memory deviceand the second type of non-volatile memory device comprises a spintorque transfer magneto-resistive random access memory device (STT-MRAM)comprising a free layer, a barrier layer, and a reference layer; and themonolithic integrated circuit further comprising a bit line electricallyconnected to the STT-MRAM device via the free layer.
 16. The monolithicintegrated circuit of claim 13, wherein: a magnetic tunnel junctiontransistor of the STT-MRAM device is disposed at a second interconnectlayer; and a bit line connected to the STT-MRAM device is at a thirdinterconnect layer.
 17. A monolithic integrated circuit, comprising: adevice layer including one or more logic transistors, wherein each ofthe one or more logic transistors comprises a corresponding source, acorresponding drain, and a corresponding gate; a first side interconnectlayer above the device layer; a second side interconnect layer below thedevice layer; a first type of non-volatile memory device in the firstside interconnect layer; and a second type of non-volatile memory devicein the second side interconnect layer, the second type of non-volatilememory device different from the first type of non-volatile memorydevice, wherein one of the first or second type of non-volatile memorydevice is connected to a gate.
 18. The monolithic integrated circuit ofclaim 17, wherein one of the first type of non-volatile memory deviceand the second type of non-volatile memory device comprises a resistiverandom access memory (RRAM) device, and wherein the RRAM devicecomprises: a first electrode; a second electrode; and a switching layerbetween the first electrode and the second electrode.
 19. The monolithicintegrated circuit of claim 18, further comprising: an oxygen exchangelayer between the switching layer and the second electrode; and a bitline connected to the RRAM device via the second electrode.
 20. Themonolithic integrated circuit of claim 17, wherein another of the firstor second type of non-volatile memory device is connected one of asource or a drain.